A recent trend in the dynamic random access memory ("DRAM") technology includes addition of operating from a single external system clock signal. Such DRAMs are called synchronous DRAMs or SDRAMs. This single external system clock signal is routed to several locations within the integrated circuit memory. This routing of the clock signal, along with associated circuitry in which it passes through, causes delay. Yet, it is necessary that several components of the integrated circuit memory SDRAM function in a synchronous manner, and such delay can effect this operation.
In particular, this delay adversely effects the apparent access time of an SDRAM. The apparent access time of an SDRAM is measured from the single external system clock signal input to valid data output. It is referred to the "apparent" access time, because it is the time "seen" by a system employing the SDRAM. For example, the access time for an output stage of an SDRAM during a read operation is typically measured from a positive edge of the single external system clock signal to the appearance of valid data at the outputs. Thus, the single external system clock signal is used to start an access (either a read or a write) and to clock data (either out or in).
In an effort to reduce apparent access time of the SDRAM, it has been proposed in the prior art that either a phase-lock-loop or delay-lock-loop (PLL or DLL) be added in-chip to the SDRAM. (By "in-chip" it should be understood to mean that the referenced circuitry is included in the SDRAM chip; "off-chip" means just the opposite of in-chip.) This PLL or DLL circuitry is to allow for internal generation of an "early" clock signal, namely, a signal which leads the single external system clock signal. This early clock signal may then be used to clock data to be read ("read data") out of the SDRAM. Because access time internal to an SDRAM is measured from an early clock signal in such a configuration, external or apparent access time measured from an external system or main clock signal will be reduced. The effectiveness and advantages of the proposed SDRAM are not necessarily known.
However, there are several problems which may be associated with adding either a PLL or DLL type of circuitry in-chip to an SDRAM. First, additional standby current for the SDRAM may be required. Second, additional time for powering up and for locking the SDRAM may be needed. Third, adding a PLL or DLL type of circuitry in-chip may be costly and may add too much complexity to the SDRAM. For example, by adding such PLL or DLL devices more wafer area will be consumed, and difficult to implement shielding may be needed to avoid locking onto a wrong signal or noise, such as beat frequency. Lastly, including PLL or DLL circuitry on an SDRAM results in repeated circuitry for systems having more than one SDRAM.
Consequently, it would be desirable to provide an alternative to the addition of PLL or DLL circuitry in-chip to an SDRAM to control access timing.